The present invention relates in general to an improvement for digital electronic circuits. More particularly, the present invention relates to a new and improved apparatus and method for removing glitches from a clock signal used to time the operations of a digital circuit.
In digital communications, it is often necessary to time the operations of the digital communication circuits with a clock signal. In particular, clock signals are used to synchronize the transfer of digital information between various locations. These clock signals can be derived in a number of different ways. In the simplest case, there exists a source such as a crystal, oscillator, etc. that produces the clock signal and is referred to as a clock. The clock generates a sequence of clock pulses that are normally equally spaced and of equal duration. These sequences of pulses are used to time and control the digital circuitry that makes up a communications device.
The pulse width of the clock pulses utilized by digital circuits is typically selected to be as small as possible while remaining consistent with the operating characteristics of the digital circuit. The period of the clock pulses is selected according to the speed at which the digital circuit must operate. The major restriction is that the clock period minus the pulse width must be large enough to allow the digital circuit to shift to its new state before the next clock pulse occurs. If this restriction is not met, the digital circuit will not have a sufficient amount of time to change states correctly.
In any electronic system, noise, interference and electrostatic discharges (ESD) can create additives to electric signals in the system. These additives are often referred to as glitches and may affect any portion of an electronic circuit. Thus, it is possible that these additives or glitches may affect the clock signal in the system. Consequently, the clock signal may not meet the clock period minus pulse width restriction discussed above. Because digital circuits rely heavily upon a consistent clock pulse to time their state transitions and operations, a glitch in the clock of digital circuit may disable the functioning of the electronic circuit entirely.
Digital designers have used analog filters composed of resistors and capacitors to attempt to filter the clock signal and remove glitches that may occur. However, these prior art analog filters are deficient in a number of respects. In particular, analog filters can only remove clock glitches of a certain width for which they must be designed. Therefore, what is needed is an improved method and apparatus for removing glitches that allows glitches of any width to be removed.
A preferred embodiment of the present invention provides an apparatus for removing glitches from a first clock signal produced by a first clock. The apparatus includes a high-speed clock that produces a second clock signal. The first clock signal and the second clock signal are preferably synchronous and the second clock signal has a frequency that is greater than the first clock signal. More particularly, the high-speed clock has a period that is less than either the normal high or low time of the first clock signal. A counter maintains a count in accordance with the second clock signal. A first comparator compares the count kept by the counter to a compare value. The compare value is a binary number that is N bits in width and the second clock signal has a period T such that the maximum duration of a glitch that can be removed by the apparatus is given by the equation 2N*T. Preferably, the compare value may be manually or automatically adjusted. The count is reset if the count is equal to the compare value. A second comparator determines if a first value of the first clock signal is equal to a second value of the first clock signal and resets the counter if the first value is not equal to the second value. A first memory stores a first value of the first clock signal and replaces the first value of the first clock signal with a second value of the first clock signal if the first value is not equal to the second value. A second memory receives the stored value from the first memory and outputs the stored value as a valid transition in the first clock signal when the first comparator determines that the count is equal to the compare value. The first memory and the second memory are preferably D flip-flops that are driven by the high-speed clock.
Glitches in electronic circuits due to noise or interference are undesirable in that they may cause the circuit to malfunction, lock up or produce inaccurate and unpredictable results. This is especially true when the glitch occurs in a clock signal that is being used to synchronize the functioning of the electronic circuit. The above described apparatus provides a new and useful way to remove glitches from a clock signal. Furthermore, the apparatus can be constructed from relatively simple and inexpensive electronics and adapted for use in a wide variety of environments. Thus, the present invention is a substantial improvement upon the prior art.
In a selected embodiment, the present invention further encompasses a method of removing glitches in a clock signal caused by noise or interference. The method begins with the receiving of the clock signal. The clock signal is monitored by sampling the clock signal in accordance with a second clock signal and comparing consecutive samples of the clock signal to determine if a transition in the clock signal has occurred. A count is initiated in accordance with the second clock signal, which has a period that is less than the clock signal, when a first transition in the clock signal is detected. The first transition is output as a valid transition in the clock signal if the count reaches a predetermined number. The count is reset if a second transition is detected prior to the count equaling the predetermined number. The count is also reset when the count reaches the predetermined number. The predetermined number may be manually or automatically altered.
In yet another method performed in accordance with the present invention, glitches are detected in a first clock signal by detecting a time period between transitions in the first clock signal. The detected time period is then compared with an expected time period to determine if the transition in the first clock signal was valid. The expected time period is preferably equal to an expected period of the first clock signal. A glitch-free clock signal is output every time a valid transition in said first clock signal occurs.
By comparing the time between transitions in a clock signal with an expected time period for the clock signal, the above described method is able to distinguish between valid and invalid transitions in the clock signal. A glitch-free clock signal can then be output every time a valid transition is detected. In this manner, glitches are effectively removed from the clock signals and the deleterious effects of the glitches can be avoided. Therefore, in its various embodiments, the present invention is an improvement upon the prior art.